The present invention relates to technology for verifying logic circuits and relates in particular to a characterization device and a computer program thereof for extracting the characteristics of hard macros such as SRAM (Static Random Access Memories).
Progress made in recent years in developing semiconductor integrated circuits containing many functions as well as more advanced functions has led to the mounting of hard macros such as CPU (central processing units) peripheral I/O, and SRAM onto a single semiconductor chip. These types of semiconductor devices require a technique for characterizing (extracting characteristics) of the hard macro such as a SRAM at high speed. Technology relating to this topic is described in the patents disclosed in the following four patent documents.
The technology disclosed in Japanese Unexamined Patent Application Publication No. Hei9 (1997)-179888 has the goal of providing a timing verification method for performing timing verification with high precision and moreover with a low cost CPU. This method investigates the input time of each data signal and clock signal as well as the distortion on each input waveform, inputs the respective variables for each function corresponding to the input waveform distortion for each clock signal and data signal, and calculates the respective data signal delay times and clock signal delay times. The method then calculates the difference in arrival times between data signals and clock signals within the internal nodes of data storage elements within the logic circuits, from the input times for each data signal and clock signal and from the data signal delay time and clock signal delay time. Moreover, the method also compares the timing constraint values with the difference in arrival times, and detects timing constraint violations in the data signal and the clock signal input times.
The technology disclosed in Japanese Unexamined Patent Application Publication No. Hei10 (1998)-222545 has the goal of providing a parameterized memory circuit reduction method and logic cell library generating method for extracting parameterized memory characteristic values in a short time and with high precision. This method extracts the parasitic capacitance and parasitic resistance of the transistors in the leaf cell during generation of a net list for leaf cells from layout data for the parameterized memory, and substitutes the leaf cell into an equivalent reduced circuit. During generation of an equivalent circuit for the overall memory by combining the above described leaf cells, the method in Japanese Unexamined Patent Application Publication No. Hei10 (1998)-222545 removes those sections not affecting calculation of characteristics, and also makes reductions by simplifying sections that affect the characteristic calculation. This method then generates a net list for a circuit simulation operation including input vectors and analysis conditions, implements the circuit simulation, and based on results from that simulation automatically generates a logic cell library for calculating the characteristics.
The technology disclosed in Japanese Unexamined Patent Application Publication No. 2003-218216 has the object of measuring the input setup and hold timing values for input terminals of function macros such as memories physically located within the semiconductor integrated circuit with good accuracy. This method establishes selector circuits and FF circuits, fixes the external clock signal and external input signal timing for states at which the function macros operate normally, selects the clock terminal 2 signal for the function macro in the selector circuit, detects the timing for applying transitions in the FF circuit output while offsetting the phase of the clock measurement signals in the FF circuit. This method then observes the timing Tb for measurement clock signals at each time point, selects the input terminal signal for the function macros in the selector circuit, detects the timing for applying transitions in the FF circuit output while shifting (offsetting) the phase of the clock measurement signals in the FF circuit, observes the timing Ta for measurement clock signals at each point, and calculates the difference between the timing Ta and Tb.
The technology disclosed in Japanese Unexamined Patent Application Publication No. 2006-350548 has the object of reducing the circuit simulation count needed for forming a timing library for circuits containing a large number of input/output paths, and reducing the time needed to generate the timing library. If the timing library generator device is making a timing library comprised of 4-bit register circuits, then a simulation is made of all operating conditions contained in the timing library, for just a portion of the 1 bit registers, and then forms the timing library from the timing constraint values or delay values obtained from those results, that also serve as other 1 bit register delay values and timing constraint values. This simulation performed on a portion of the 1 bit registers first of all performs a simulation for four of the 1 bit registers on a portion of operating conditions among the plurality of operating conditions included in the timing library, and then selects the largest timing constraint values and delay values found among these conditions.
In the technology that is disclosed in Japanese Unexamined Patent Application Publication No. Hei 9 (1997)-212541, the static timing verification unit implements a static timing verification using techniques in the related art by searching the first type block connection information, clock information, and data input timing information for the first type block. The test pattern generator unit generates an input test pattern for executing a dynamic timing verification on the second type block based on the static timing verification results and clock information. The dynamic timing verification unit then makes a dynamic timing verification based on the input test pattern for the second type block.